1. Field of the Invention
The present invention relates to a computer control system, and more particularly, to a rapid resolution priority determination among several contenders for a communication bus.
2. Description of the Prior Art
In the art relating to computer control system, and particularly to systems wherein industrial processes are controlled by a digital computer, the system usually includes a basic computer or central processor unit and a number of peripheral units. The peripheral units may include a plurality of process control stations for directly controlling a phase of the industrial process and/or responsive to measured process variables. Additionally, the peripheral units may include recorders or other memory devices, or data manipulating structure. All of these peripheral units must have access to the central processor at one time or another. Such access is usually accomplished by means of a communication bus which may include a number of groups of wire lines, one group being dedicated to address information, one group to intelligence information and others to control function information. In order that utter chaos does not prevail, means must be provided for controlling the access to the bus in accordance with a predetermined arrangement. Numerous schemes have been provided for effecting such control, exemplary of which is U.S. Pat. No. 3,886,524. Among the schemes provided for such control are polling schemes wherein the central processor polls the individual peripheral devices, in a predetermined sequence, to ascertain if any has a request for access to the bus. The central processor then grants access to the bus to one of the peripheral devices in accordance with a predetermined priority schedule.
In another type of scheme, a control signal is generated which is transmitted serially to the peripheral devices, wherein the order of priority is determined by the serial order of the devices along the serial string.
In the implementation of such computer systems, there is usually a separate buffer controller between each of the peripheral devices and the communication bus. These buffer controllers are usually on a circuit card inserted in predetermined slots in a card cage. In the first type of access control system, the address of a particular peripheral device is correlated with a predetermined one of the slots in the card cage. In other words, the central processor addresses a particular slot of the card cage to access a selected peripheral device.
In the second type of scheme referenced above, while the selecting address may well be on the individual card, the serial relationship imposes a restriction on the card slot arrangement. Since there is a requirement for the serial connection, the cards must be put into the slots in their priority order, beginning at the first slot with no gaps in the slots between the first and last card.
In both of these schemes, considerable time is required for the procedure of actually accessing the selected peripheral device to the communication bus.